Any mainframe such as a S/390 compatible system, which uses a storage protection (SP) key and uses a command response (handshake) type bus between the processor and memory, provides an interface to memory or main store. Processor to memory (or Main Store MS) interfaces have always existed in the computer industry. There are many ways to define the communication protocol or handshake between the sender and receiver on both sides of the bus for memory accesses. A typical example of processor to memory protocol includes Command Accept, Fetch Data Alert, Store Complete with additional protocols for bus management if the data bus is a bi-directional bus.
These protocols may require separated hardware signals or the protocol may be embedded with an existing bus and time shared control signals are passed with other existing signals like data bus or command bus signals. These other solutions require extra hardware signal lines and/or restrict the performance in order to mix with control signals on an existing bus which can handle the interface handshake. Separated hardware signals means more hardware lines and more input/output (IO) from chips and modules. Timing sharing with other signals also presents a restriction and limits functional usage.